1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device for nonvolatilely writing data in accordance with application of a voltage to a variable resistive element.
2. Description of the Related Art
In recent years, attention has been focused on a variable resistive memory as a succeeding candidate of a flash memory. Herein, the variable resistive memory devices include a variable resistive memory (ReRAM: Resistive RAM) in a narrow sense that nonvolatilely stores the resistance value state of a transition metal oxide element as the recording layer, and a phase change memory (PCRAM: Phase Change RAM) that utilizes the resistance value information in a crystalline state (conductor) and an amorphous state (insulator) using a chalcogenide element as the recording layer.
It is well known that the variable resistive elements of the variable resistive memory have two kinds of operation modes. One of the modes is called a bipolar type of setting a high-resistance state and a low-resistance state by switching the polarity of applied voltage. The other is called a unipolar type of setting the high-resistance state and the low-resistance state by controlling the voltage value and the voltage application time without switching the polarity of applied voltage. To realize a high density memory cell array, the unipolar type is preferred. In the case of the unipolar type, a cell array can be configured by disposing a variable resistive element and a rectifier element such as a diode at each intersection of word lines and bit lines without using a transistor. Further, a large capacity of memory can be realized by laminating and arranging such memory cell array in three dimensions without increasing the cell array area (refer to JP-A-2005-522045).
In performing a set operation of writing data, a reset operation of erasing data and a read operation of reading data in the memory cell array provided on a semiconductor substrate, a certain processing time is required. Particularly, the reset operation has a longer voltage application time required and takes a longer time for processing than the set operation. To increase the speed of the processing of the variable resistive memory device in the reset operation, it is required to increase the number of memory cells to make the reset operation in parallel within the memory cell array. However, as the number of memory cells to make the reset operation is greater, a voltage drop due to a parasitic resistance of the wiring within the memory cell array increases. Due to this voltage drop, it is not possible to apply sufficient voltage and current to the memory cells, whereby there is a risk that the reset operation is not performed for the desired memory cell.